This application claims the benefit of Korean Patent Application Nos. 1998-34893, filed on Aug. 27, 1998 and 1999-1125, filed on Jan. 15, 1999, which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a method for forming a polycrystalline thin layer and a thin-film transistor(xe2x80x9cTFTxe2x80x9d) for a liquid crystal display device.
2. Description of the Related Art
A thin film transistor for an active matrix liquid crystal display can be classified into an amorphous silicon TFT or a polycrystalline silicon TFT in accordance with the kind of the active layer used therein. The polycrystalline silicon TFT is advantageous in that the surface of a polycrystalline silicon layer has a fewer defects than that of the amorphous silicon, thus the polycrystalline silicon TFT has a faster mobility characteristic.
A conventional method for forming a polycrystalline silicon layer for TFT will be described with reference to FIGS. 1A through 1D. A buffer layer 12 made of silicon oxide is deposited on a substrate 10 as shown in FIG. 1A. Then, an amorphous silicon layer 14 is formed on the buffer layer 12 as shown in FIG. 1B. The amorphous silicon layer 14 is then converted into a polycrystalline silicon layer 14P through a laser annealing process as shown in FIG. 1C. The crystallization is performed from silicon seeds to polycrystalline silicon with plurality of grains 17 and the grain boundaries 19, which protrude from the relatively flat surface of grains 17. The crystallized polycrystalline silicon layer 14P is used as an active layer of TFT. In order to induce electric charges for the active layer of TFT and for the purpose of insulating the active layer from a gate electrode, which will be formed over the active layer, a silicon oxidation layer 16 is formed thereon using PECVD (Plasma Enhanced Chemical Vapor Deposition) or APCVD (Atmosphere Pressure Chemical Vapor Deposition), as shown in FIG. 1D.
The electric characteristics of polycrystalline silicon TFT, e.g. mobility of electric charges and threshold voltage, are affected by density of trap energy states of interfaces 20 between the silicon oxidation layer 20 and the polycrystalline silicon layer 14P. The density of trap energy is affected by excessive heat energy of the annealing process.
One method of reducing density of trap energy states is suggested. Before the laser annealing process, the silicon oxidation layer is deposited on the amorphous silicon layer and oxygen ions are implanted into the amorphous silicon layer. The reaction between implanted oxygen ions and the amorphous silicon atoms forms silicon oxidation layer, which reduce the state density of trap energy of the interfaces.
However, since relatively large oxygen ions are forcibly implanted into the amorphous silicon layer without any chemical reaction, the oxygen ions damage the atom arrangement of the amorphous silicon layer and act as impure elements. The impurities of the interfaces adversely affect the mobility of the electron charges on the surface of the polycrystalline silicon layer and the reliability of the TFT.
Therefore an object of the present invention is to provide a method for fabricating TFT which can reduce impurities and mismatches between silicon oxidation layer and the polycrystalline silicon layer.
Another object of the present invention is to provide a method for forming a polycrystalline silicon layer which can reduce impurities therein.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
According to one preferred embodiment of the present invention, a method for forming a polycrystalline silicon layer includes the steps of depositing an amorphous silicon layer and a silicon oxidation layer on a substrate in the listed order; and implanting semiconductor ions into the amorphous silicon layer and the silicon oxidation layer while heating the substrate, thereby converting the amorphous silicon layer into a polycrystalline silicon layer, and forming an amorphous oxidation layer between the amorphous silicon layer and the silicon oxidation layer.
During the ion implantation the substrate is preferably being heated at a temperature between 200 to 500xc2x0 C. The ions for the implantation are preferably chosen from a group comprising of Si (silicon), Ge (germanium), Te (tellurium), Sb (Antimony), As (Arsenic), and Ga (Gallium).
The method further includes the steps of removing the silicon oxidation layer; and annealing the amorphous oxidation layer thereby converting the amorphous oxidation layer into a crystallized oxidation layer.
According to another preferred embodiment of the present invention, a method for fabricating a thin-film transistor includes the steps of: forming an amorphous silicon layer and a silicon oxidation layer on a substrate in the listed order; implanting semiconductor ions into the amorphous silicon layer and the silicon oxidation layer while heating the substrate, thereby converting the amorphous silicon layer into a polycrystalline silicon layer, and forming an amorphous oxidation layer between the amorphous silicon layer and the silicon oxidation layer; removing the silicon oxidation layer; annealing the amorphous oxidation layer thereby converting the amorphous oxidation layer into a crystallized oxidation layer; forming a gate electrode on the crystallized oxidation layer; forming a source region, a drain region, and a channel region in the polycrystalline silicon layer; and forming a source electrode and a drain electrode which contact the source region and the drain region, respectively.
According to another preferred embodiment of the present invention, a method for fabricating a thin-film transistor includes the steps of: forming a source electrode and a drain electrode on a substrate; depositing a first insulating layer on the source and the drain electrodes; forming an amorphous silicon layer and a silicon oxidation layer on the first insulating layer; implanting semiconductor ions into the amorphous silicon layer and the silicon oxidation layer while heating the substrate, thereby converting the amorphous silicon layer into a polycrystalline silicon layer, and forming an amorphous oxidation layer between the amorphous silicon layer and the silicon oxidation layer; removing the silicon oxidation layer; annealing the amorphous oxidation layer thereby converting the amorphous oxidation layer into a crystallized oxidation layer; forming a gate electrode on the crystallized oxidation layer; forming a source region, a drain region, and a channel region in the polycrystalline silicon layer; and forming a first connecting electrode to connect the source region and the source electrode and a second connecting electrode to connect the drain region and the drain electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.